49 research outputs found
High-Performance FPGA Implementation of Equivariant Adaptive Separation via Independence Algorithm for Independent Component Analysis
Independent Component Analysis (ICA) is a dimensionality reduction technique
that can boost efficiency of machine learning models that deal with probability
density functions, e.g. Bayesian neural networks. Algorithms that implement
adaptive ICA converge slower than their nonadaptive counterparts, however, they
are capable of tracking changes in underlying distributions of input features.
This intrinsically slow convergence of adaptive methods combined with existing
hardware implementations that operate at very low clock frequencies necessitate
fundamental improvements in both algorithm and hardware design. This paper
presents an algorithm that allows efficient hardware implementation of ICA.
Compared to previous work, our FPGA implementation of adaptive ICA improves
clock frequency by at least one order of magnitude and throughput by at least
two orders of magnitude. Our proposed algorithm is not limited to ICA and can
be used in various machine learning problems that use stochastic gradient
descent optimization
Modeling and Propagation of Noisy Waveforms in Static Timing Analysis
A technique based on the sensitivity of the output to input waveform is
presented for accurate propagation of delay information through a gate for the
purpose of static timing analysis (STA) in the presence of noise. Conventional
STA tools represent a waveform by its arrival time and slope. However, this is
not an accurate way of modeling the waveform for the purpose of noise analysis.
The key contribution of our work is the development of a method that allows
efficient propagation of equivalent waveforms throughout the circuit.
Experimental results demonstrate higher accuracy of the proposed
sensitivity-based gate delay propagation technique, SGDP, compared to the best
of existing approaches. SGDP is compatible with the current level of gate
characterization in conventional ASIC cell libraries, and as a result, it can
be easily incorporated into commercial STA tools to improve their accuracy.Comment: Submitted on behalf of EDAA (http://www.edaa.com/
C-SAR: SAT Attack Resistant Logic Locking for RSFQ Circuits
Since the development of semiconductor technologies, exascale computing and
its associated applications have required increasing degrees of efficiency.
Semiconductor-transistor-based circuits (STbCs) have struggled in increasing
the GHz frequency. Emerging as an alternative to STbC, the superconducting
electrons (SCE) technology promises higher-speed clock frequencies at ultra-low
power consumption. The rapid single flux quantum (RSFQ) circuits have a
theoretical potential for three orders of magnitude reduction in power while
operating at clock frequencies higher than 100 GHz. Although the security in
semiconductor technology has been extensively researched and developed, the
security design in the superconducting field requires field demands attention.
In this paper, C-SAR is presented that aims to protect the superconducting
circuit electronics from Boolean satisfiability (SAT) based attacks. The SAT
attack is an attack that can break all the existing combinational logic locking
techniques. C-SAR can immunize against SAT attacks by increasing the key search
space and prolonging the clock cycles of attack inputs. Even in the worst case
of C-SAR, in face of S-SAT a specially designed SAT attack, C-SAR can also soar
the attack cost exponentially with key bits first, then linearly with the
length of camouflaged DFF array. We have shown in this work that the cost of
C-SAR is manageable as it only linearly increases as a function of key bits
SANSCrypt: A Sporadic-Authentication-Based Sequential Logic Encryption Scheme
We propose SANSCrypt, a novel sequential logic encryption scheme to protect
integrated circuits against reverse engineering. Previous sequential encryption
methods focus on modifying the circuit state machine such that the correct
functionality can be accessed by applying the correct key sequence only once.
Considering the risk associated with one-time authentication, SANSCrypt adopts
a new temporal dimension to logic encryption, by requiring the user to
sporadically perform multiple authentications according to a protocol based on
pseudo-random number generation. Analysis and validation results on a set of
benchmark circuits show that SANSCrypt offers a substantial output
corruptibility if the key sequences are applied incorrectly. Moreover, it
exhibits an exponential resilience to existing attacks, including SAT-based
attacks, while maintaining a reasonably low overhead.Comment: This paper has been accepted at the 28th IFIP/IEEE International
Conference on Very Large Scale Integration (VLSI-SoC